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| White Electronic Designs 4MB SYNCHRONOUS CARD EDGE DIMM FEATURES 4x128Kx64 Synchronous Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns Flow-Through Architecture Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Aysnchronous Output Enable (G#) Internally self-timed Write Gold Lead Finish 3.3V +10%, -5% Operation Access Speed(s): tKHQV = 9.5, 10, 11, 12, 15ns Common Data I/O High Capacitance (30pf) drive, at rated Access Speed Single total array Clock Multiple Vcc and GND EDI2GG464128V DESCRIPTION The EDI2KG64128VxxD is a Synchronous SRAM, 60 position Card Edge DIMM (120 contacts) Module, organized as 4x128Kx64. The Module contains eight (8) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Synchronous Only, Flow-Through, Early Write Device. This module provides High Performance, Ultra Fast access times at a cost per bit benefit over BiCMOS Asynchronous SRAM based devices. As well as improved cost per bit, the use of Synchronous or Synchronous Burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement. Synchronous operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. All read and write operations to this module are performed on Quad Words (64 bit operations). Write cycles are internally self timed and are initiated by a rising clock edge. This feature relieves the designer the task of developing external write pulse width circuitry. PIN NAMES DQ0-DQ63 A015 E1#, E2#, E3#, E4# CK GW# G# Vcc Vss NC Input/Output Bus Address Bus Synchronous Bank Enables Array Clock Synchronous Global Write Enable Asynchronous Output Enable 3.3V Power Supply Ground No Connect *This product is subject to change without notice. October 2004 Rev. 1 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 EDI2GG464128V VSS A0 A1 A2 A3 VCC A4 A5 A6 A7 VSS A8 VSS CK VSS E4# VCC E3# G# VSS DQ0 DQ1 DQ2 DQ3 VCC DQ8 DQ9 DQ10 DQ11 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ24 DQ25 DQ26 DQ27 VSS DQ32 DQ33 DQ34 DQ35 VCC DQ40 DQ41 DQ42 DQ43 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ56 DQ57 DQ58 DQ59 VSS VSS A16 A15 A14 A13 VCC A12 A11 A10 A9 VSS RFU VSS NC VSS E2# VCC E1# GW# VSS DQ7 DQ6 DQ5 DQ4 VCC DQ15 DQ14 DQ13 DQ12 VSS DQ23 DQ22 DQ21 DQ20 VCC DQ31 DQ30 DQ29 DQ28 VSS DQ39 DQ38 DQ34 DQ37 VCC DQ47 DQ46 DQ45 DQ44 VSS DQ55 DQ54 DQ53 DQ52 VCC DQ63 DQ62 DQ61 DQ60 VSS October 2004 Rev. 1 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM EDI2GG464128V A0-16 GW# G# 128Kx32 GW# G# E# CLK DQ 128Kx32 GW# G# E# CLK DQ E1# 128Kx32 GW# G# E# CLK DQ 128Kx32 GW# G# E# CLK DQ E2# 128Kx32 GW# G# E# CLK DQ 128Kx32 GW# G# E# CLK DQ E3# 128Kx32 GW G# E# CLK DQ 128Kx32 GW G# E# CLK DQ E4# DQ0-63 CLK October 2004 Rev. 1 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN DESCRIPTIONS DIMM Pins 3, 5, 7, 9, 13, 15, 17, 19, 20, 23, 18, 16, 14, 10, 8, 6 38 27 36, 32, 35, 31 37 Various Various Various Symbol Type Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Input/Output Supply Ground Description EDI2GG464128V A0-A15 Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle. Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Bank Enables: These active LOW inputs are used to enable each individual Synchronous bank and to gate ADSP#. Output Enable: This active LOW asynchronous input enables the data output drivers. Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64. Core power supply: +3.3V -5%/+10% Ground GW# CK E1#, E2# E3#, E4# G# DQ0-63 Vcc Vss October 2004 Rev. 1 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs SYNCHRONOUS ONLY - TRUTH TABLE Operation Synchronous Write-Bank 1 Synchronous Read-Bank 1 Synchronous Write-Bank 2 Synchronous Read-Bank 2 Synchronous Write-Bank 3 Synchronous Read-Bank 3 Synchronous Write-Bank 4 Synchronous Read-Bank 4 Snooze Mode E1# L L H H H H H H X E2# H H L L H H H H X E3# H H H H L L H H X E4# H H H H H H L L X GW# L H L H L H L H X EDI2GG464128V G# H L H L H L H L X CK DQ High-Z High-Z High-Z High-Z X High-Z ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Relative to Vss VIN Storage Temperature Operating Temperature (Commercial) Operating Temperature (Industrial) Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55C to +125C 0C to +70C -40C to +85C 20 mA RECOMMENDED DC OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Input Low Input Leakage Output Leakage Output High IOH = -4ma Output Low IOL = 8ma Sym VCC VSS VIH VIL ILI ILO VOH VOL Min 3.14 0.0 2.2 -0.3 -2 -2 2.4 Typ 3.3 0.0 3.0 0.0 1 1 Max 3.6 0.0 VCC + 0.3 0.8 2 2 0.4 Units V V V V A A V V * Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS - READ CYCLE Description Power Supply Current Power Supply Current Device Selected, No Operation Snooze Mode CMOS Standby Clock Running-Deselect *TBD Symbol Icc1 Icc IccZZ Icc3 IccK Typ 1.55 .75 200 400 600 9.5 2.8 1.8 300 500 900 10 2.2 1.5 300 500 900 Max 11 2.2 1.3 300 500 900 12 2.7 1.3 300 500 900 15 2.0 1.0 300 500 900 Units A A mA mA mA AC TEST LOAD DQ Z0 == 50 Z0 50W AC TEST CONDITIONS Parameter Input Pulse Levels Input and Output Timing Ref. Output Test Equivalencies I/O Vss to 3.0V 1.25 See figure at left Unit V V V 50 Vt = 1.25V Figure 1 - Output Load Equivalent October 2004 Rev. 1 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs READ CYCLE TIMING PARAMETERS Description Clock Cycle Time Clock High Time Clock Low Time Clock to Output Valid Clock to Output Invalid Clock to Output Low-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Enable to Output High-Z Address Setup Bank Enable Setup Address Hold Bank Enable Hold *TBD EDI2GG464128V Sym tKHKH tKHKL tKLKH tKHQV tKHQX1 tKHQX tGLQV tGLQX tGHQZ tAVKH tEVKH tKHAX tKHEX 9.5ns Min * * * * * * * * * * * * * Max * * * * * * * * * * * * * 2.5 2.5 1.0 1.0 0 3 2 Min 12 5 5 10ns Max Min 12 5 5 10 3 2 4 0 4 2.5 2.5 1.0 1.0 11ns Max Min 15 5 5 11 3 2 5 0 5 2.5 2.5 1.0 1.0 12ns Max Min 20 6 6 12 3 2 5 0 5 2.5 2.5 1.0 1.0 15ns Max Units ns ns ns 15 ns ns ns 6 ns ns 5 ns ns ns ns ns WRITE CYCLE TIMING PARAMETERS Description Clock Cycle Time Clock High Time Clock Low Time Address Setup Address Hold Bank Enable Setup Bank Enable Hold Global Write Enable Setup Global Write Enable Hold Data Setup Data Hold *TBD Sym tKHKH tKHKL tKLKH tAVKH tKHAX tEVKH tKHEX tWVKH tKHWX tDVKH tKHDX 9.5ns Min * * * * * * * * * * * Max * * * * * * * * * * * Min 12 5 5 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0 10ns Max Min 12 5 5 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0 11ns Max Min 15 5 5 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0 12ns Max Min 20 6 6 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0 15ns Max Units ns ns ns ns ns ns ns ns ns ns ns October 2004 Rev. 1 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION Part Number EDI2GG464128V95D* EDI2GG464128V10D* EDI2GG464128V11D EDI2GG464128V12D EDI2GG464128V15D* *Consult Factory for Availability EDI2GG464128V Organization 4x128Kx64 4x128Kx64 4x128Kx64 4x128Kx64 4x128Kx64 Voltage 3.3 3.3 3.3 3.3 3.3 Speed (ns) 9.5 10 11 12 15 Package 120 Card Edge DIMM 120 Card Edge DIMM 120 Card Edge DIMM 120 Card Edge DIMM 120 Card Edge DIMM Height* 28.58 (1.125") 28.58 (1.125") 28.58 (1.125") 28.58 (1.125") 28.58 (1.125") PACKAGE DESCRIPTION: 120 LEAD CARD EDGE DIMM 89.23 (3.513) MAX. 5.33 (0.210) MAX. 28.58 (1.125) MAX. 4.95 (0.195) 1.04 0.05 (0.041 0.002) 1.88 0.08 (0.074 0.003) 31.75 (1.250) 3.81 (0.150) 1.27 (0.050) TYP. 5.08 (0.200) TYP. 5.08 (0.200) MIN. 41.91 (1.650) 44.70 0.05 (1.760 0.002) 34.54 0.08 (1.360 0.003) R 0.78 (0.031) (2x) R6 R5 R3 R2 ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). October 2004 Rev. 1 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 4MB SYNCHRONOUS CARD EDGE DIMM EDI2GG464128V Revision History Rev # Rev 0 History Created Release Date July 1999 Status Rev 1 Corrected block diagram specs 10-25-04 October 2004 Rev. 1 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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